1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a color filter on thin film transistor type in-plane switching mode liquid crystal display device.
2. Discussion of the Related Art
A liquid crystal display (LCD) device has been widely used for a television and a monitor because of its superiority in displaying a moving image and high contrast ratio. In general, the LCD device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. The LCD device includes a liquid crystal panel having two substrates and a liquid crystal layer between the two substrates. The liquid crystal molecules in the liquid crystal layer are re-aligned by an electric field. Accordingly, the alignment of the liquid crystal molecules is changed in accordance with the direction of the electric field and the light transmittance of the liquid crystal panel is changed, thereby the image displayed.
Among various types LCD devices, an active matrix type liquid crystal display (AM-LCD) device has been the subject of recent research due to its high resolution and superior quality for displaying a moving image.
In the LCD device, the liquid crystal layer is driven by a vertical electric field generated between the two substrates. Although the LCD device using the vertical electric field provides a superior transmittance and a high aperture ratio, the LCD device has a narrow viewing angle. Accordingly, various other types of LCD devices having wide viewing angles, such as an in-plane switching (IPS) mode LCD device, have been developed.
FIG. 1 is a cross-sectional view of an in-plane switching mode liquid crystal display device according to the related art. In FIG. 1, a lower substrate 1 and an upper substrate 3 face and are spaced apart from each other. A liquid crystal layer 5 is interposed between the lower and the upper substrates 1 and 3. The lower substrate 1 and the upper substrate 3 may be referred to as an array substrate and a color filter substrate, respectively. A pixel electrode 23 and a common electrode 25 are formed on the lower substrate 1. The liquid crystal layer 5 is driven by a horizontal electric field “L” between the pixel electrode 23 and the common electrode 25.
Although not shown in FIG. 1, a gate line, a data line and a thin film transistor (TFT) are formed on an inner surface of the lower substrate 1, and a black matrix and a color filter layer are formed on an inner surface of the upper substrate 3. The lower and upper substrates 1 and 3 are attached to each other by a seal pattern including an epoxy resin.
When the lower and upper substrates 1 and 3 are attached to each other, light leakage may be generated and aperture ratio of the IPS mode LCD device may be reduced due to misalignment of the lower and upper substrates 1 and 3, i.e., attachment error. As a result, the IPS mode LCD device is fabricated based on a margin of attachment error. Specifically, since the black matrix is formed to have a width greater than a designed width based on the margin of attachment error, the aperture ratio of the IPS mode LCD device is further reduced.
For the purpose of improving the aperture ratio, a thin film transistor on color filter (TOC) type LCD device and a color filter on thin film transistor (COT) type LCD device where a TFT and a color filter layer are formed on a single substrate have been the subject of recent research.
FIG. 2 is a cross-sectional view showing an array substrate for a color filter on thin film transistor type in-plane switching mode liquid crystal display device according to the related art. In FIG. 2, a gate line (not shown), a common line 2 and a data line 4 are formed on a substrate 10. The common line 2 is spaced apart from and parallel to the gate line, and the data line 4 crosses the gate line to define a pixel region P. An outermost common electrode 6 extending from the common line 2 is formed at an edge portion of the pixel region P.
A thin film transistor (TFT) Tr connected to the gate line and the data line 4 includes a gate electrode 11, a gate insulating layer 13, a semiconductor layer 15, a source electrode 17 and a drain electrode 19. The drain electrode 19 extends to overlap the common line 2. The overlapped portion of the common line 2 as a first capacitor electrode 2a, the overlapped portion of the drain electrode 19 as a second capacitor electrode 19a and the gate insulating layer between the first and second capacitor electrodes 2a and 19a as a dielectric layer constitute a storage capacitor StgC.
A passivation layer 21 is formed on the TFT Tr, and a black matrix 30 of a black resin is formed on the passivation layer 21. The black matrix 30 corresponds to the gate line, the data line 4 and the TFT Tr. A color filter layer 33 including red, green and blue color filters is formed on the black matrix 30 and the passivation layer 21. The red, green and blue color filters are disposed in the pixel region P sequentially and repeatedly. An overcoat layer 35 is formed on the black matrix 30 and the color filter layer 33, and a pixel electrode 24 and a common electrode 26 are formed on the overcoat layer 35. The overcoat layer 35 and the color filter layer 33 have a drain contact hole 27 exposing the drain electrode 19 of the TFT Tr. The pixel electrode 23 is electrically connected to the drain electrode 19 through the drain contact hole 27.
In the color filter on thin film transistor (COT) type in-plane switching (IPS) mode liquid crystal display (LCD) device, the black matrix 30 prevents mixing of colors by the red, green and blue color filters to improve contrast ratio. In addition, the black matrix 30 shields incident light to the TFT Tr to prevent malfunction of the TFT Tr. For the sufficient light shielding property, the black matrix 30 is required to have an optical density equal to or greater than about 4.0, preferably, equal to or greater than about 5.0. When the black matrix 30 is formed of the black resin, the black matrix 30 has a thickness of about 1 μm to about 2 μm for the optical density equal to or greater than about 4.0.
Further, the color filter layer 33 is formed to overlap an edge portion of the relatively thick black matrix 30 and a step difference is generated at the edge portion of the relatively thick black matrix 30. The subsequent process such as a rubbing process may be deteriorated due to the step difference. Accordingly, the overcoat layer 35 is formed on the color filter layer 33 and the black matrix 30 to prevent deterioration due to the step difference. However, the fabrication process is complicated and fabrication cost increases by the overcoat layer 35.
The black matrix 30 is formed by pattering a resin layer colored with a black pigment such as a carbon black. The black matrix 30 of a black resin has a resistivity equal to or smaller than about 1×107 Ωcm. Accordingly, when the black matrix 30 is disposed over a conduction line such as the gate line, the data line 4 and the common line 2, a resistive-capacitive (RC) delay is caused in the conduction line and display quality is deteriorated due to a cross-talk.
FIGS. 3A and 3B are pictures showing resistive-capacitive delay and deterioration in display quality, respectively, of a color filter on thin film transistor type in-plane switching mode liquid crystal display device according to the related art.
In FIGS. 3A and 3B, first and second data signals DS1 and DS2 correspond to upper and lower portions UP and LP of the COT type IPS mode LCD device. When the black matrix 30 is formed on the data line 4, the second data signal DS2 is delayed as compared with the first data signal DS1 such that rising and falling times of the second data signal DS2 are longer than rising and falling times of the first data signal DS1. As a result, the image of the lower portion LP has poor display quality, e.g., low contrast ratio and low brightness, as compared with the image of the upper portion UP. Accordingly, the COT type IPS mode LCD device has non-uniform display quality.